The present invention generally relates to semiconductor integrated circuits, and more particularly to a semiconductor integrated circuit having an improved testing function. The present invention is suited for application to a direct memory access controller, for example.
In a system which uses a high-speed cathode ray tube (CRT) or an input/output device such as hard disk and floppy disk drives, a large number of data transfers is generated. But a high-speed transfer cannot be expected if the data transfers are successively processed by software according to a programmable input output (PIO) system. Hence, a direct memory access (DMA) transfer system is generally employed for making such a large number of data transfers.
According to the DMA transfer system, a central processing unit (CPU) sets a source address, a destination address, and a number of words to be transferred into a register within a DMA controller (DMAC) prior to the data transfer. When the DMA transfer is started thereafter, the DMAC carries out the data transfers depending on transfer requests of input/output devices. At the same time as the data transfer, the DMAC processes in parallel the source address and the destination address and also carries out processes such as a calculation of the number of words transmitted and a discrimination of a transfer termination. For this reason, it is possible to make the data transfers at a high speed. In addition, the processing capability of the system as a whole increases because the CPU can carry out other processes during the data transfers which are controlled by the DMAC.
On the other hand, as an integration density of large scale integrated (LSI) circuits increases, internal functions of the DMAC are improved thereby making an internal random logic of the DMAC extremely complex. Hence, there is a proposed DMAC having a programmable logic array (PLA) structure in which the complex internal logic is developed into systematic AND and OR planes to facilitate the designing of the DMAC.
However, although full functions are obtainable by the high integration density and the designing facility of the DMAC is improved by employing the PLA structure in the conventional DMAC, there are problems from the point of view of a testing efficiency of the DMAC.
In other words, when actually testing the DMAC, terminals of the DMAC and a testing device are connected, for example. A known test data are written into the DMAC and then read out from the DMAC to be compared with anticipated values in the testing device. But as the functions of the DMAC improve, a number of the test data greatly increases. As a result, the test efficiency is poor in the conventional DMAC in which test cycles related to one test data span a relatively large number of cycles.
FIGS.1(A) through 1(H) are timing charts for explaining test cycles of the conventional DMAC. FIGS.1(A) and 1(B) respectively show clock signals .phi.1 and .phi.2. FIG.1(C) shows a command M2-0 which is entered into the DMAC from the testing device and includes a slave write (W) command and a slave read (R) command. FIGS.1(D), 1(E), and 1(F) respectively show states ABUS, DBUS, and dbus of an external address bus which connects the DMAC and the testing device, an external data bus which connects the DMAC and the testing device, and an internal data bus within the DMAC. FIGS.1(G) and 1(H) respectively show states STmem and outLT of a data holding memory within the DMAC and an output latch which temporarily holds the data of the data holding memory and outputs the data to the internal data bus if needed.
The test data are written as follows. In a cycle A, the testing device sets the command M2-0 to the slave write (W) command. In a cycle B, the write address is transferred on the external address bus ABUS, and an nth write data (test data) "W DATA n" is transferred on the external data bus DBUS. In a cycle C, the nth write data "W DATA n" is entered on the internal data bus and this write data is written into the data holding memory which is in a precharge time Pre during this cycle C.
On the other hand, the test data are read out as follows. In a cycle D, the data (for example, the previously written nth data) within the data holding memory at a read address designated by the testing device is read out when the data holding memory enters a discharge time Dis, and a read out data "R DATA n" is held in the output latch. In a cycle E, the read out data "R DATA n" is outputted on the internal data bus and is further outputted on the external data bus in a cycle F.
Therefore, according to the conventional DMAC, at least the six cycles A through F are required to write one test data and output the read out data onto the external data bus. Hence, there is a problem in that the test efficiency of the conventional DMAC is poor.